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TMS320C5515
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
www.ti.com
3.2.1.3
LDO Control
All three LDOs can be simultaneously disabled via software by writing to either the BG_PD bit or the
LDO_PD bit in the RTCPMGT register (see Figure 5-26 ). When the LDOs are disabled via this
mechanism, the only way to re-enable them is by asserting the WAKEUP signal pin (which must also have
been previously enabled to allow wakeup), or by a previously enabled and configured RTC alarm, or by
cycling power to the CV DDRTC pin. Note: CV DDRTC must be externally powered. None of the on-chip LDOs
can be used to power CV DDRTC .
ANA_LDO: The ANA_LDO is only disabled by the BG_PD and the LDO_PD mechanism described above.
Otherwise, it is always enabled.
DSP_LDO: The DSP_LDO can be statically disabled by the DSP_LDO_EN pin as described in
Section 3.2.1.2 , LDO Outputs . It can be also dynamically disabled via the BG_PD and the LDO_PD
mechanism described above. The DSP_LDO can change its output voltage dynamically by software via
the DSP_LDO_V bit in the LDOCNTL register (see Figure 3-1 ). The DSP_LDO output voltage is set to 1.3
V at reset.
USB_LDO: The USB_LDO can be independently and dynamically enabled or disabled by software via the
USB_LDO_EN bit in the LDOCNTL register (see Figure 3-1 ). The USB _LDO is disabled at reset.
Table 3-3 shows the ON/OFF control of each LDO and its register control bit configurations.
50
Device Configuration
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